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02/05/2013
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Digital Verification Engineer
Empresa: Dialog Semiconductor
Localização: Alemanha
Working as a Digital Verification Engineer with Dialog youll find yourself in a truly international environment where your skills and experience are recognised, rewarded and
Department: Audio
Location: Kirchheim/Teck-Nabern
Country: Germany
Job Number: DIALOG00660
Job Type: Permanent
What we can offer
We have a fantastic opportunity for a Digital Verification Engineer to join our award-winning and rapidly growing team at Dialog Semiconductor.
Working as a Digital Verification Engineer with Dialog you’ll find yourself in a truly international environment where your skills and experience are recognised, rewarded and challenged on a daily basis, as well as have access to a variety of internal and external training opportunities to help you develop your career and reach your full potential. In addition we are committed to supporting the health and wellbeing of our employees, offering the chance to participate in pension and medical plans (where local culture and practice supports this) and a selection of ‘well-being’ initiatives across a number of our locations (e.g. flu vaccination programme and a cycle to work scheme).
The Role
Working in our Digital Design team in Kirchheim/Teck, you will:- Participate in the specification phase for power-management digital control circuits with focus on verification
- Block, top and system level design verification using advanced verification methodologies and implementing test benches and test cases.
- Develop coverage driven verification plan and maintain feedback to ensure Vplan and specification are kept in sync
- Develop verification process to achieve >95% functional coverage, through directed, constrained random, and formal verification techniques.
- Support applications of UVM based techniques, creating UVM components, assertions, properties and checkers
- Support application of verification activity into Device validation with Applications group
- Ensure support scripts, documents and Tool reports are generated for progress reviews.
- Develop/maintaining project regression suite
- Support and mentor junior verification engineers
What we are looking for
At Dialog you will be successful if you are self-motivated, delivery-focused and passionate about helping us become the go-to company for integrated mixed-signal and analog differentiated power saving technologies!
You could be perfect for this particular role if you have:
- 2 or more years of experience in the digital design verification
- Degree in electrical engineering, computer science or comparable
- Fluent in Verilog and SystemVerilog
- Knowledge of OVM/VMM or UVM, and object orientated approach to Test bench development
- Experience with constrained random techniques, ABV and scoreboard implementation
- Experience with both RTL and Gatelevel simulation.
- Strong Design background and experienced in reading RTL code and hardware design as well as good overall knowledge in the digital design process
- Concise and proactive communication skills within a multi-site and multi-cultural environment and contributing to a successful team environment
- Command of written and verbal English
- Willingness to travel
- Takes responsibility for solutions and makes them happen
- Looking for continuous improvement in own and Dialog work practices
- Confident and proactive attitude about own role and contribution to company goals
Desirable
- Experience with Cadence ePlanner/eManager tool flow.
- Understanding of analogue/ mixed signal IC design and behavioural modeling.
Join Us!
If this role is of interest, then it’s time we heard from you! If you have any queries, please contact the Recruiter for this role,Tomasz Stoklosa (tomasz.stoklosa@diasemi.com) who will be happy to help.
If you have heard enough to confirm that Dialog is the company for you, click below and apply now!
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